AD74122 a rev. prg 1/03 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 2003 low cost, low power stereo audio codec preliminary technical data preliminary technical data features 2.5v stereo audio codec with 3.3 v tolerant digital inter- face supports 8khz to 48 khz sample rates supports 16/20/24-bit word lengths multibit sigma delta modulators with ?perfect differential linearity restoration? for reduced idle tones and noise floor data directed scrambling dacs - least sensitive to jitter performance (20 hz to 20 khz) 85 db adc dynamic range 93 db dac dynamic range digitally programmable input/output gain on-chip volume controls per output channel software controllable clickless mute supports 256xfs, 512xf s and 768xfs master mode clocks master clock pre-scaler for use with dsp master clocks on-chip reference 20-lead tssop package applications digital video camcorders (dvc) portable audio devices (walkman, pdas etc.) audio processing voice processing telematic systems general purpose analog i/o functional block diagram general description the AD74122 is a front-end processor for general purpose audio and voice applications. it features two multi-bit ? a/d conversion channels and two multi-bit ? d/a conversion chan- nels. the adc channels provide >70 db snr and the dac channels provide >80db snr both over an audio signal band- width. the AD74122 is particularly suitable for a variety of applica- tions where stereo input and output channels are required, including audio sections of digital video camcorders, portable personal audio devices and telematic applications. its high qual- ity performance also make it suitable for speech and telephony applications such as speech recognition and synthesis and mod- ern feature phones. an on-chip reference voltage is included but can be overdriven by an external reference source if required. the AD74122 offers sampling rates which, depending on mclk selection and mclk divider ratio, range from 8 khz in the voiceband range to 48 khz in the audio range. the AD74122 is available in 20 lead tssop package option and is specified for the automotive temperature range of -40c to +105c. ??
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?2? rev. prg AD74122?specifications (avdd =2.5v 5%, dvdd2 = 2.5v 5%, dvdd1 = 2.5v 5%, f clkin = 12.288 mhz, f samp = 48 khz, t a = t min to t max , unless otherwise noted) preliminary technical data AD74122 parameter min typ max units test conditions analog-to-digital converters adc resolution 24 bits signal to noise ratio (snr) 70 77 db dynamic range (20 hz to 20 khz, -60 db input) no filter 85 db f s =48khz 78 85 db f s =16khz with a-weighted filter 92 db f s =48khz total harmonic distortion + noise -67 db f s =48khz -75 db f s =16khz programmable input gain 12 db gain step size 3 db offset error -55 30 80 mv gain error -1.5 db full scale input voltage 0.5 vrms input resistance 10 k input capacitance 15 pf common mode input volts 1.125 v crosstalk 100 db adc input signal= 1.0khz, 0db; dac output=dc digital-to-analog converters dac resolution 24 bits signal to noise ratio (snr) 80 89 db dynamic range (20 hz to 20 khz, -60 db input) no filter 93 db f s =48khz 84 93 db f s =16khz with a-weighted filter 95 db f s =48khz total harmonic distortion + noise -88 db f s =48khz -88 -81 db f s =16khz dc accuracy offset error -75 10 50 mv gain error -1.0 0.2 1.0 db volume control step size (1023 linear steps) 0.098 % volume control range (max attenuation) 60 db mute attenuation -100 db de-emphasis gain error +/- 0.1 db full scale output voltage 0.5 vrms output resistance 145 common mode output volts 1.125 v crosstalk 95 db adc input signal=agnd; dac output level=1.0khz, 0db reference (internal) absolute voltage, v ref 1.125 v v ref tc tbd ppm/c
?3? rev. prg AD74122 preliminary technical data AD74122 parameter min typ max units test conditions adc decimation filter 1 f s =48khz pass band 21.5 khz pass band ripple 0.2 mdb transition band 5 khz stop band 26.5 khz stop band attenuation 120 db group delay 910 s low group delay mode 87 s dac interpolation filter 1 f s =48khz pass band 21.5 khz pass band ripple 10 mdb transition band 5 khz stop band 26.5 khz stop band attenuation 75 db group delay 505 s low group delay mode 55 s logic input v inh , input high voltage dvdd1 - 0.8 dvdd1 v v inl , input low voltage 0 0.8 v input current -10 +10 a input capacitance 10 pf logic output v oh , output high voltage dvdd1 - 0.4 dvdd1 v v ol , output low voltage 0 0.4 v three-state leakage current -10 +10 a power supplies avdd 2.375 2.75 v dvdd2 2.25 2.75 v dvdd1 2.25 3.36 v power supply rejection ratio 1khz, 300mv p-p signal at analog supply pins 72 db 50/60hz, 300mv p-p signal at analog supply pins 73 db notes 1 guaranteed by design specifications subject to change without notice. table i. current summary (avdd= 2.5v; dvdd1=2.5v; dvdd2=2.5v) conditions avdd dvdd1 dvdd2 total current current current current (max) adc, reference, ref-amp on tbd tbd tbd dac, reference, ref-amp on tbd tbd tbd reference, ref-amp on tbd tbd tbd all sections on tbd tbd tbd tbd powerdown mode tbd tbd tbd tbd notes all values are typical unless otherwise noted. max values are quoted with dvdd1=3.6v sample rates quoted are for 16khz and (48khz)
?4? rev.pr g AD74122?specifications (avdd =2.5v 5%, dvdd2 = 2.5v 5%, dvdd1 = 2.5v 5%, f clkin = 12.288 mhz, f samp = 48 khz, t a = t min to t max , unless otherwise noted) preliminary technical data parameter min max unit comments master clock and reset t mh mclk high 25 ns t ml mclk low 25 ns t res reset low 20 ns t rs din setup time 5 mclks to reset rising edge 1 t rh din hold time 5 mclks to reset rising edge 1 serial port t fd dfs delay 5 ns from dclk rising edge 2 t fs dfs setup time 5 ns to dclk fallingedge t fh dfs hold time 5 ns from dclk falling edge t dd dout delay 5 ns from dclk rising edge t ds din setup time 10 ns to dclk falling edge t dh din hold time 10 ns from dclk falling edge t dt dout three-state 25 ns from dclk rising edge mclk t mh t ml t res t rs t rh din figure mclk and reset timing msb msb-1 t ds t dh t fs t fh t fd t dd dfs dclk din dout msb msb-1 msb-2 msb-2 t ch t cl figure . serial port timing dvdd1 2 i ol 100a i oh to outp ut pin c l 50 pf 100a figure . load circuit for digital output timing specification
AD74122 ? 5 ? rev. prg preliminary technical data caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD74122 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pre- cautions are recommended to avoid performance degradation or loss of functionality. ordering guide model range package AD74122yru -40oc to +105oc ru-20 absolute maximum ratings * (t a = 25c, unless otherwise noted.) avdd, dvdd2 to agnd, dgnd ?0.3 v to +3.0 v dvdd1 to agnd, dgnd -0.3 v to +4.5 v agnd to dgnd ?0.3 v to +0.3 v digital i/o voltage to dgnd ?0.3 v to dvdd1 + 0.3 v operating temperature range automotive (y version) ?40c to +105c storage temperature range -65c to +150c junction temperature 150c temperature range parameter min max unit specifications guaranteed -40 +105 oc storage -65 +150 oc 20 lead tssop, ja thermal impedance 150.4c/w lead temperature, soldering vapour phase (60 sec) 215c infrared (15 sec) 220c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability.
AD74122 ?6? rev.prg preliminary technical data pin function description pin no. mnemonic i/o description 1 dclk i/o data port serial clock 2 din i data port serial data input. the state of din on the rising edge of reset determines the operating mode of the interface, see data port interface section for more information 3 dfs i/o data port frame synchronisation signal 4 dout o data port serial data output i powerdown/reset input 6 avdd analog power supply connection 7 capn2 filter capacitor for channel 2 (right channel) negative 8 capp2 filter capacitor for channel 2 (right channel) positive 9 voutl o analog output - left channel 10 vinr i analog input - right channel 11 vinl i analog input - left channel 12 voutl o analog output - right channel 13 capp1 filter capacitor for left channel (positive) 14 capn1 filter capacitor for left channel (negative) 15 refcap i/o internal reference decoupling capacitor - can also be used for connection of an external reference 16 agnd analog ground connection 17 dgnd digital ground connection 19 dvdd2 digital power supply connection (core) 19 dvdd1 digital power supply connection (interface) 20 mclk i external master clock input pin configuration 20-lead tssop (ru-20) vinl voutr cappl cappr refcap agnd dgnd dvdd2 dvdd1 mclk vinr voutl capnl capnr avdd dout dfs din dclk 1 2 3 20 4 19 5 18 6 17 7 16 8 15 9 14 10 13 12 11
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AD74122 ? 7 ? rev. prg preliminary technical data functional description general description the AD74122 is a 2.5v stereo codec. it comprises two adc and two dac channels with single ended inputs and outputs. signal conditioning and programmable gain stages are also provided. each of these sections are described in further detail below. the AD74122 is controlled by means of a flexible serial interface port (sport) which can be programmed to accomodate many industry standard dsps and microcontrollers. the AD74122 can be set to operate as a
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figure . adc and dac engine master or slave device. the AD74122 can also be set to operate with sample rates of 8khz to 48khz depending on the values of mclk and the mclk prescalers. on chip digital filtering is provided for the dac and adc channels with a low group delay option to reduce the delays through the filters when operating at lower sample rates. figure shows a block diagram of a dac and adc channel in the AD74122. figure shows a block diagram of the filter arrangement of the adc and dac filters.
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4- 3 3 3 & 3 !6 .!-4 #7 4- figure . dac filter section adc section there are two adc channels in the AD74122, configured as a stereo pair. each adc channel can be independently muted under software control. each adc has single input pin with additional pins for decoupling/filter capacitors. each adc channel has an independent input amplifier gain stage which can be programmed in steps of +3db, from 0db to +12db. the input amplifier gain settings are set by programming the appro- priate bits in control register e for the left adc and control register h for the right adc. the AD74122 input channels employ a multi-bit sigma-delta conversion technique, which provides a high resolution output with system filtering being implemented on-chip. sigma-delta converters employ a tech- nique known as over-sampling, where the sampling rate is many times the highest frequency of interest. the oversampling ratio for the adc is 64 and a decimation filter is used to reduce the output to standard sample rates. the maximum sample rate is 48khz. adc capp and capn pins the adc channel requires two external capacitors to act as charge resevoirs for the switched capacitor inputs of the sigma- delta modulator. these capacitors isolate the outputs of the pga stage from glitches generated by the sigma-delta modula- tor. the capacitor also forms a low pass filter with the output impedance of the pga (approximately 124 which helps to isolate noise from the modulator engine. the capacitors should be of good quality such as npo or polyproplene film and values from 100pf to 1nf are suitable. peak readback the AD74122 can store the highest adc value from each channel in order to facilatate level adjustment of the input signal. programming the peak enable bit in control register h with a 1 will enable adc peak level reading. the peak values are stored as a 6 bit number from 0db to -63db in 1db steps. reading control register f and i will give the highest adc values for the left adc and right adc re- spectively, since the bit was set. the adc peak registers are automatically cleared after reading. decimator section the digital decimation filter has a passband ripple of 0.002db and a stopband attenuation of 120db. the filter is an fir type with a linear phase response. the group delay at 48khz is 910us. output sample rates up to 48 khz are sup- ported. input signal swing each adc input has an input range of 0.5 v rms / 1.414 v p-p about a bias point equal to v refcap (see figure ). the analog input can also be ac coupled to the AD74122 as shown which will automatically bias the signal to the v refcap value internally. this allows signals biased around a voltage other than v refcap to be connected directly to the AD74122.
9 51 10nf npo 47f figure .input swing dac section the AD74122 has two dac channels arranged as a stereo pair, with two, single-ended, analog outputs. each channel has it?s own independently programmable attenuator. control register g controls the attenuation factor for the left dac while con- trol register j controls the attenuation factor for the right dac. each of these registers is 10 bits wide giving 1024 steps of attenuation. AD74122 output channels employ a multi-bit sigma-delta conversion technique, which provides a high qual- ity output with system filtering being implemented on-chip. output signal swing each dac input has an output range of 0.5 v rms / 1.414 v p-p (single-ended) about a bias point equal to v refcap (see figure )
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AD74122 ? 9 ? rev. prg preliminary technical data low group delay it is possible to bypass much of the digital filtering by enabling the low group delay function in control register c. by re- ducing the amount of filtering the AD74122 applies to input and output samples the time delay between the sampling inter- val and when the sample is available is greatly reduced. this can be of benefit in applications such as telematics where mini- mal time delays are important. when the low group delay function is enabled the sample rate becomes imclk/128. reference the AD74122 features an on-chip reference whose nominal value is 1.125 v. a 10 nf capacitor applied at the refcap pin is necessary to stabilise the referrence. (see figure )
): );: figure if it is required an external reference can be used as the refer- ence source of the adc and dac sections. this may be desir- able in situations where multiple devices are required to use the same value of reference or because of a better temperature coefficient specifications. the internal reference can be dis- abled via control register a and the external reference applied at the refcap pin (see figure ). external references should be of a suitable value such that the voltage swing of the inputs or outputs is not effected by being too close to the power supply rails. figure master clocking scheme the update rate of the AD74122?s adc and dac channels require an internal master clock (imclk) which is 256 times that sample update rate (imclk = 256 * f s ). in order to provide some flexibility in selecting sample rates, the device has a series of three master clock pre-scalers which are program- mable and allow the user to choose a range of convenient sample rates from a single external master clock. the master clock signal to the AD74122 is applied at the mclk pin. the mclk signal is passed through a series of three programmable mclk pre-scalers (divider) circuits which can be selected to reduce the resulting internal mclk (imclk) frequency if required. the first and second mclk pre-scalers provides divider ratios of /1 (pass through), /2, /3 while the third pre- scaler provides divider ratios of /1 (pass through), /2, /4. imclk programmable mclk divider control reg /1 /2 /3 /1 /2 /4 pre-scaler 2 pre-scaler 3 mclk /1 /2 /3 pre-scaler 1 figure the divider ratios will allow more convenient sample rate selection from a common mclk which may be required in many voice related applications. control register b should be programmed to achieve the desired divider ratios. selecting sample rates the sample rate at which the convertor runs is always 256 times the imclk rate. imclk is the internal master clock and is the output from the master clock prescaler. the de- fault sample rate is 48khz (based on an external mclk of 12.288mhz). in this mode the adc modulator is clocked at 3.072mhz and the dac modulator is clocked at 6.144mhz.. sample rates which are lower than 256 x mclk can be acheived by using the mclk prescaler. example 1: f samp = 48 khz and 8 khz required mclk = 48*10 3 * 256 = 12.288 mhz to cater for 48 khz f samp for f samp = 8 khz, it is necessary to use the /3 setting in pre- scaler 1, the /2 setting in pre-scaler 2 and pass through in pre- scaler 3. this results in an imclk = 8*10 3 * 256 = 2.048 mhz (= 12.288 mhz/6). example 2: fsamp = 44.1 khz and 11.025 khz required mclk = 44.1*10 3 * 256 = 11.2896 mhz to cater for 44.1 khz f samp for f samp = 11.025 khz, it is necessary to use the /1 setting in pre-scaler 1 and the /4 setting in pre-scaler 2 and pass through in pre-scaler 3. this results in an imclk = 11.025*10 3 * 256 = 2.8224 mhz (= 11.2896 mhz/4). reseting the AD74122 the AD74122 can be reset by bringing the reset pin low. following a reset the internal circuitry of the AD74122 en- sures that the internal registers are reset to their default set- tings and the on-chip ram is purged of previous data samples. the din pin is sampled to determine if the AD74122 is re- quired to operate in master or slave mode. the reset process takes 3072 mclk periods and the user should not attempt to program the AD74122 during this time.
AD74122 ?10? rev. prg preliminary technical data power supplies and grounds the AD74122 features three separate supplies: avdd, dvdd1 and dvdd2. avdd is the supply to the analog section of the device and must therefore be of sufficient quality to preserve the AD74122?s performance characteristics. it is nominally a 2.5 v supply. dvdd1 is the supply for the digital interface section of the device. it is fed from the digital supply voltage of the dsp or controller to which the device is interfaced and allows the AD74122 to interface with devices operating at supplies of between 2.5 v -5% to 3.3 v + 10%. dvdd2 is the supply for the digital core of the AD74122. it is nominally a 2.5 v supply. accessing the internal registers the AD74122 has 10 registers which can be programmed to control the functions of the AD74122. each register is 10 bits wide and is writen to or read from using a 16 bit write or read operation with the exception of control registers f and i which are read-only. table shows the format of the data transfer operation. the control word is made up of a read/write bit, the register address and the data to be written to the device. note that in a read operation the data field is ignored by the device. access to the control regis- ters is via the serial port through one of the operating modes described below. serial port the AD74122 contains a flexible serial interface port which is used to program and read the control registers of the codec and to send and receive dac and adc audio data. the serial port is compatible with many popular dsps and can be programmed to operate in a variety of modes depending on which one best suits the dsp being used. the serial port can be set to operate as a master or slave device which is discussed below. figure shows a timing diagram of the serial port. serial port operating modes the serial port of the codec can be programmed to operate in a variety of modes depending on the requirements and flexibility of the dsp to which it is connected. the two principal modes or operation are mixed mode and data mode. mixed mode mixed mode allows for the control registers of the codec to be programmed and read back. it also allows data to be sent to the dacs and data to be read from the adcs. in mixed mode there are seperate data slots each with its own frame syncronisation signal (dfs) for control, left channel and right channel information. the codec powers up in mixed mode by default to allow the control registers to be pro- grammed. figure shows the default set- ting for mixed mode. data mode data mode can be used when programming or reading the control registers is no longer required. data mode will provide a frame synchronisation (dfs) pulse for each channel of data. once the part has been programmed into data mode the only way to change the control registers is to perform a hardware reset to put the codec back into mixed mode. figure shows the default setting for data mode. data word length the AD74122 can be programmed to send adc audio data and receive dac audio data in different word length formats of 16, 20 or 24 bits. the default mode is 16 bits but this can be changed by programming control register c for the appropri- ate word length. selecting master or slave mode the initial operating mode of the codec is determined by the state of the din pin during the first five mclks following a reset. if the din pin is high during this time slave mode is selected. in slave mode the dfs and dclk pins are inputs and the control signals for these pins must be provided by the dsp or other controller. if the din pin is low immediately following a reset the codec will operate in master mode. master mode operation in master mode the dfs and dclk pins are outputs from the codec. this is the easiest mode to use the codec in as the cor- rect timing relationship between sample rate, dclk and dfs is controlled by the codec. slave mode operation in slave mode the dfs and dclk pins are inputs to the codec. care need to be exercised when designing a system to operate the codec in this mode as the relationship between the sample rate, dclk and dfs needs to be controlled by the dsp or other controller and must be compatible with the inter- nal dac/adc engine of the codec. figure shows a block diagram of the dac engine and the codecs serial port. the sample rate for the dac engine is determined by the mclk and mclk prescalers. the dac engine will read data from the dac left data and dac right data at this rate. it is therefore important that the serial port is updated at the rate as any error between the two will accumulate and eventually cause the dac engine to resynchronise with the serial port which will cause erroneous values on the dac output pins. in most cases it is easy to keep a dsp in synchronisation with the codec if they are both run from the same clock or the dsp clock is a multiple of the codecs mclk. in this case there will be a fixed relationship between the instruction cycle time of the dsp program and the codec so a timer could be used to accu- rately control the dac updates. if a timer is not available the multi-frame-sync (mfs) mode could be used to generate a dfs pulse every 16 or 32 dclks allowing the dsp to accu- rately control the number of dclks between updates using an auto buffering or dma type technique. in all cases for slave mode operation there should be 128 dclks (normal mode) or 256 dclks (fast mode) between dac updates.the adc operates in a similar manner, however, if the dsp does not read an adc result this will only appear as a missed sample and will not be audible.
AD74122 ? 11 ? rev. prg preliminary technical data figure serial port (sport) timing msb msb-1 t 5 t 6 t 2 t 3 t 1 t 4 dfs dclk din dout msb msb-1 msb-2 msb-2 right dac data dac engine left dac data serial port dfs din load data outl outr *resync *resync is only used when the dac becomes unsynchronised with the serial port figure dac engine table serial mode selection crd:3 crd:2 crc:5,4 dm /mm dsp mode word width operating mode figure 0 0 16 16 bit data mode figure 0 1 16 32 bit data mode figure 1 0 16 16 bit mixed mode figure 1 1 16 32 bit mixed mode figure 0 0 >16 16 bit data mode figure 0 1 >16 32 bit data mode figure 1 0 >16 16 bit mixed mode figure 1 1 >16 32 bit mixed mode figure
AD74122 ?12? rev. prg preliminary technical data control (16 bits) dfs (mm16) din 1/f s dout dac left (16 bits) dac right (16 bits) adc left (16 bits) adc right (16 bits) control (16 bits) dac left (16 bits) dac right (16 bits) adc left (16 bits) adc right (16 bits) 128 dclks (normal mode) 256 dclks (fast mode) status (16 bits) status (16 bits) figure 16 bit mixed mode :word length = 16 bits control (16 bits) left dac data (24 bits) right dac data (24 bits) control (16 bits) dfs (mm16) din 1/f s 16 dclks status (16 bits) left adc data (24 bits) right adc data (24 bits) status (16 bits) dout 128 dclks (normal mode) 256 dclks (fast mode) figure 16 bit mixed mode: word length = 24 bits dac left (16 bits) dfs din 1/f s dout dac right (16 bits) adc right (16 bits) dac left (16 bits) dac right (16 bits) adc right (16 bits) 128 dclks (normal mode) 256 dclks (fast mode) adc left (16 bits) adc left (16 bits) figure 16 bit data mode : word length = 16 bits left dac data (24 bits) right dac data (24 bits) dfs (mm16) din 1/f s 16 dclks left adc data (24 bits) right adc data (24 bits) dout 128 dclks (normal mode) 256 dclks (fast mode) left dac data (24 bits) left adc data (24 bits) figure 16 bit data mode : word length = 24 bits
AD74122 ? 13 ? rev. prg preliminary technical data control (16 bits) right dac (16 bits) control (16 bits) din dfs 1/f s 32 dclks status (16 bits) left adc (16 bits) right adc (16 bits) status (16 bits) dout left dac (16 bits) 128 dclks (normal mode) 256 dclks (fast mode) figure 32 bit mixed mode : word length = 16 bits control (16 bits) right dac (24 bits) control (16 bits) din dfs 1/f s 32 dclks status (16 bits) left adc (24 bits) right adc (24 bits) status (16 bits) dout left dac (24 bits) 128 dclks (normal mode) 256 dclks (fast mode) figure 32 bit mixed mode : word length = 24 bits left dac (16 bits) din dfs 1/f s 32 dclks dout left dac data (24 bits) left adc data (24 bits) 128 dclks (normal mode) 256 dclks (fast mode) right dac (16 bits) right adc (16 bits) left adc (16 bits) figure 32 bit data mode : word length = 16 bits left dac data (24 bits) right dac data (24 bits) din dfs 1/f s 32 dclks left adc data (24 bits) right adc data (24 bits) dout left dac data (24 bits) left adc data (24 bits) 128 dclks (normal mode) 256 dclks (fast mode) figure 32 bit data mode : word length = 24 bits
AD74122 ?14? rev. prg preliminary technical data 1/f s 32 dclks cl r slr cl r slr dfs din dout figure . mutli frame sync 32 bit mixed mode 1/f s 32 dclks l dfs din dout l r r l l r r figure . mutli frame sync 32 bit data mode 1/f s 16 dclks clr cr dfs din dout l slr slr figure . mutli frame sync 16 bit mixed mode 1/f s 16 dclks lr r dfs din dout l lr lr figure . mutli frame sync 16 bit data mode table multi frame sync selection crd:9 crd:3 crc:2 mfs dm/mm dsp mode operating mode figure 1 0 0 16 bit data mode figure 1 0 1 32 bit data mode figure 1 1 0 16 bit mixed mode figure 1 1 1 32 bit mixed mode figure
AD74122 ? 15 ? rev. prg preliminary technical data table . control register map address(binary) name description type width reset setting 0000 cra control register a r/w 10 tbd 0001 crb control register b r/w 10 tbd 0010 crc control register c r/w 10 tbd 0011 crd control r egister d r/w 10 tbd 0100 cre control register e r/w 10 tbd 0101 crf control register f r 10 tbd 0110 crg control register g r/w 10 tbd 0111 crh c ontrol register h r/w 10 tbd 1000 cri control register i r 10 tbd 1001 crj c ontrol register j r/w 10 tbd bit field description 15 r /w when this bit is high the contents of the data field will be written to the register specified by the address field. when this bit is low a read of the register specified by the address field will occur at the next sample interval. the contents of the data field are ignored. 14-11 register address this 4-bit field is used to select one of the 12 control registers of the AD74122. 10 reserved this bit is reserved and should always be programmed with zero. 9-0 data field this 10-bit field holds the data the is to be written to or read from the register specified in the address field. table <>control word description /w address res data field 15 14,13,12,11 10 9, 8, 7, 6 , 5 ,4, 3, 2, 1, 0 w address res function adcr input amplifier adcr dacr adcl input amplifier adcl dacl reference reference amplifier reset reserved 15 14,13,12,11 10 9 8 7 6 5 4 3 2 1 0 1 0000 0 0=off 1=on 0=off 1=on 0=off 1=on 0=off 1=on 0=off 1=on 0=off 1=on 0=off 1=on 0=off 1=on 0=default 1=reset 0 table . control register a
AD74122 ?16? rev. prg preliminary technical data table . control register b / r w s s e r d d as e rfn o i t c n u r o t a l u d o m c d a k c o l c r o t a l u d o m c a d k c o l c s e rk l c m d r i h t r e d i v i d k l c m d n o c e s r e d i v i d k l c m t s r i f r e d i v i d 5 11 1 , 2 1 , 3 1 , 4 10 19 8 6 , 74 , 52 , 30 , 1 101 0 004 6 = 0 f s 2 3 = 1 f s 8 2 1 = 0 f s 4 6 = 1 f s 01 y b e d i v i d = 0 0 2 y b e d i v i d = 1 0 4 y b e d i v i d = 0 1 1 y b e d i v i d = 1 1 1 y b e d i v i d = 0 0 2 y b e d i v i d = 1 0 3 y b e d i v i d = 0 1 1 y b e d i v i d = 1 1 1 y b e d i v i d = 0 0 2 y b e d i v i d = 1 0 3 y b e d i v i d = 0 1 1 y b e d i v i d = 1 1 table . control register c w address res function reserved dac & adc wo rd wi dt h low group delay dac de -emphas is adc high pass filter 15 14,13,12,11 10 9,8,7,6 5,4 3 2,1 0 1 0010 0 0 00=16 bits 01=20 bits 10=24 bits 11=24 bits 0=disabled 1=enabled 00=none 01=44.1khz 10=32khz 11=48khz 0=disabled 1=enabled table . control register d w address res function multi frame sync reserved dm/mm dsp mode fast dclk master/ 15 14,13,12,11 10 9 8,7,6,5,4 3 2 1 0 1 0011 0 0 = normal mode 1= mfs mode 0 0 = data mode 1 = mixed mode 0=16 bits 1= 32 bits 0=128 f s 1= 256 f s 0=slave 1=master / r w s s e r d d as e rfn o i t c n u d e v r e s e rk a e p l c d a e l b a n e n i a g l c d al c d a e t u m l c a d e t u m 5 11 1 , 2 1 , 3 1 , 4 10 16 , 7 , 8 , 952 , 3 , 41 0 11 00 00 0 d e l b a s i d = 0 e l b a n e k a e p = 1 b d 0 = 0 0 0 b d 3 = 1 0 0 b d 6 = 0 1 0 b d 9 = 1 1 0 b d 2 1 = x x 1 l a m r o n = 0 e t u m = 1 l a m r o n = 0 e t u m = 1 table . control register e
AD74122 ? 17 ? rev. prg preliminary technical data table . control register f w address res function re s e rve d adcl input pe ak le ve l 15 14,13,12,11 10 9,8,7,6 5,4,3,2,1,0 0 0101 0 0 000000 = 0dbfs 000001 = -1dbfs 000010 = -2dbfs 111110 = -62dbfs 111111 = -63dbfs table . control register g w address res function dacl volume 15 14,13,12,11 10 9,8,7,6,5,4,3,2,1,0 0 0110 0 0000000000 = 0dbfs 0000000001 = (1023/1024)dbfs 0000000010 =(1022/1024)dbfs 1111111110 = (2/1024)dbfs 1111111111 = (1/1024)dbfs table . control register h w address res function reserved adcr peak enable adcr gain adcr mute dacr mute 15 14,13,12,11 10 9,8,7,6 3 4,3,2 1 0 1 0111 0 0 0=disabled 1=peak enable 000=0db 001=3db 010=6db 011=9db 1xx=12db 0=normal 1=mute 0=normal 1=mute w address res function re s e rve d adcr input pe ak le ve l 15 14,13,12,11 10 9,8,7,6 5,4,3,2,1,0 0 0101 0 0 000000 = 0dbfs 000001 = -1dbfs 000010 = -2dbfs 111110 = -62dbfs 111111 = -63dbfs table . control register i
AD74122 ?18? rev. prg preliminary technical data table . control register j w address res function dacr volume 15 14,13,12,11 10 9,8,7,6,5,4,3,2,1,0 1 1001 0 0000000000 = 0dbfs 0000000001 = (1023/1024)dbfs 0000000010 =(1022/1024)dbfs 1111111110 = (2/1024)dbfs 1111111111 = (1/1024)dbfs shrink small outline ic (tssop) (ru-20)
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